Analog Layout
Design and layout of analog ICs including op-amps, ADCs, PLLs and mixed-signal blocks, with FinFET process exposure.
Full Syllabus
What you'll learn
From process fundamentals through interview-ready portfolio work.
Foundations & Devices
✓Introduction to Analog IC design flow and Cadence Virtuoso Layout Editor
✓Understanding CMOS process technology, PDKs, and design rules (DRC)
✓Layout of MOSFETs, resistors, capacitors, and other analog devices
✓Device matching techniques including Common Centroid, Interdigitation, and Dummy structures
✓Floorplanning, routing, shielding, and power planning for analog circuits
Verification, Practice & Careers
✓Layout implementation of current mirrors, differential pairs, operational amplifiers, and comparators
✓Physical verification using DRC, LVS, ERC, and parasitic extraction (PEX)
✓Best practices for FinFET technologies, ESD protection, and latch-up prevention
✓Hands-on projects using industry-standard Cadence Virtuoso tools
✓Interview preparation with real-world design examples and industry-focused assignments
Cadence VirtuosoLVS / DRCFinFET 6nm