If you've studied digital electronics, you already understand what a chip is supposed to do. Physical Design is the discipline that decides how a chip is built — the step where an abstract description of logic gates and connections becomes an actual, manufacturable pattern of silicon and metal.
It sits right after RTL design and synthesis, and right before the chip goes to fabrication. If RTL design is like writing a detailed blueprint of a building, Physical Design is the construction phase — deciding where every wall, pipe, and wire actually goes, so the building can physically be built.
The Physical Design flow, step by step
A synthesised netlist — a list of logic gates and how they connect — goes through several stages before it's ready for manufacturing:
1. Floorplanning
This is where the chip's overall layout gets decided: where large functional blocks sit, where the power grid runs, and where input/output pins are placed. Get floorplanning wrong, and every later stage becomes harder — it's the equivalent of deciding room layout before you build a house.
2. Placement
Every individual standard cell (the basic logic gates that make up the design) gets assigned a physical (x, y) location on the chip. Good placement tools balance two competing goals: keeping connected cells close together (to reduce wire delay) and spreading cells out enough to avoid congestion.
3. Clock Tree Synthesis (CTS)
Every clocked element in a chip needs to receive the clock signal at (almost) exactly the same time. CTS builds a carefully balanced tree of buffers that distributes the clock signal across the whole chip while minimising skew — the difference in arrival time between different parts of the design.
4. Routing
Once every cell has a location, routing draws the actual metal wires that connect them, layer by layer, while obeying strict manufacturing rules about wire spacing, width, and via placement.
5. Static Timing Analysis (STA)
Throughout — and especially after routing — the design is checked against timing requirements: can every signal reach where it needs to go before the next clock edge? STA doesn't simulate the chip; it mathematically verifies every possible timing path, which is why it can catch problems simulation would miss.
6. Physical Verification and Signoff
Before a design can be sent to a fabrication plant, it has to pass a battery of checks: Design Rule Checking (DRC) confirms the layout obeys the manufacturing process's physical rules, Layout-vs-Schematic (LVS) confirms the physical layout actually matches the intended circuit, and power/IR-drop analysis confirms the chip won't have voltage problems under real operating conditions.
Why this matters for your career
Physical Design engineers are in consistent demand because this stage genuinely can't be skipped or fully automated — every chip that gets manufactured, from a simple microcontroller to a high-end processor, goes through this exact flow. It's also a field where hands-on tool experience matters as much as theory: understanding floorplanning conceptually is different from having actually floorplanned a real block and watched your timing reports improve as you fixed congestion.
That's the gap a good training program should close — not just explaining what each stage does, but putting you through the actual flow on industry-standard tools, so the concepts in this article stop being abstract.