• VLSI & Digital Design Basics – ASIC Design Flow , Digital design , Fundamentals Verilog concepts & Verilog TB
• SystemVerilog (SV) – Verilog recap, 
  SV data types, Memories, task and functions, interface, inter process communication, OOP concepts (class, inheritance, polymorphism), Constraints & randomization
• Verification Fundamentals – Directed & constrained-random testing, Testbench architecture, Scoreboards & reference models, Functional coverage basics
• UVM (Universal Verification Methodology) – UVM architecture & components, Sequences & virtual sequences, Phases & objection mechanism, Factory & configuration database, UVM RAL basics
• Assertions (SVA) – Immediate & concurrent assertions, Properties & sequences, Assertion-based verification,
• Functional Coverage – Covergroups & coverpoints, Cross coverage, Code Coverage
• Protocol Verification – AMBA protocols: APB | AHB | AXI, Protocol monitors & checkers, Industry-level debug scenarios
• Advanced DV Concepts – Low-power verification (UPF basics), GLS Basics, Clock & Reset verification, CDC fundamentals, Static verification overview, SOC basics

Tools & Skills Covered:

Hands-On Projects

• • Complete UVM Testbench Development
  • AMBA Protocol Verification Project
  • Functional & Code Coverage Closure
  • Debugging real industry-like issues

Tools Covered

• • Industry-standard simulators
  • Questa / VCS / Xcelium (conceptual & practical exposure)
  • Waveform analysis & regression concepts
  • Git basics for DV engineers